### Digital Electronics Objectives Part 15

**281 . **The Boolean expression for the logic diagram shown in Fig.47 is **πΏ=(π¨+π©)πͺ+ π©π«+π¨πͺπ«+π¬.**

**282 . ** The Boolean expression for the Karnaugh map shown below is **Y= BCD+ABC+ACD.**

**283 . ** Match the following

Boolean equation GATE

(a) A+π΅ = Y (i) OR

(b) A+B = Y (ii) NAND

(c) π΄π΅=π (iii) NOR

(d) π΄.π΅=π (iv) AND**(a) β(iii), bβ(i), (c)β(ii), (d)β(iv)**

**284 . ** The output F of the multiplexer circuit in Fig.49 can be represented by **π¨π©πͺ+ π¨π©πͺ+π¨π©πͺ.**

**285 . ** The simplified Boolean expression associated with the karnaugh map shown in fig.50 (X indicates βdonβt careβ) is **A+BC.**

**286 .** The minimum number of 2-input NAND gates required to implement the function F = (π+ π) (π+π) is **4.**

**287 .** For the circuit shown below, the output is given by **F=0.**

**288 . ** The total number of Boolean function which can be realized with four variables is **256.?**

**289 .** The Boolean expression π΄.π΅+π΄.π΅+π΄.π΅ is equivalent to **A+B.**

**290 . ** The function generated by the network is** (Eβ+ABFβ)(C+D+Fβ**

**291 . ** The Boolean expression for P will be **AB.**

**292 . ** The Boolean expression for Q will be** π¨π©+ π©π¨.**

**293 . ** The function of the circuit is that of **a half adder.**

**294 . ** ** (704)16 = (614)**8is incorrect.

**295 . ** The circuit in fig. 54 produces the output sequence **1111 1111 0000 0000.**

**296 . ** Match the following

Octal numbers Decimal equivalents

(a) 10 (i) 56

(b) 16 (ii) 14

(c) 7 (iii) 7

(d) 70 (iv) 8

(**a)—(iv), (b)β(ii), (c)β(iii), dβ(iv)**

**297 . ** Match the following

**298 .** Match the following

Binary numbers Decimal equivalents

(a) 1101 (i) 214

(b) 11011 (ii) 1316

(c) 1.0011 (iii) 27

(d) 10.01 (iv) 13**aβ(iv), bβ(iii), cβ(ii), dβ(i)**

**299 . ** For the circuit shown below, the output F is given by** F=0.**

**300 .** The minimum number of 2-input NAND gates required to implement the function F = (π+π)(π+π)**3.**