### Digital Electronics Objectives Part 15

281 . The Boolean expression for the logic diagram shown in Fig.47 is 𝑿=(𝑨+𝑩)𝑪+ 𝑩𝑫+𝑨𝑪𝑫+𝑬.

282 . The Boolean expression for the Karnaugh map shown below is Y= BCD+ABC+ACD.

283 . Match the following
Boolean equation GATE
(a) A+𝐵 = Y (i) OR
(b) A+B = Y (ii) NAND
(c) 𝐴𝐵=𝑌 (iii) NOR
(d) 𝐴.𝐵=𝑌 (iv) AND
(a) –(iii), b—(i), (c)—(ii), (d)—(iv)

284 . The output F of the multiplexer circuit in Fig.49 can be represented by 𝑨𝑩𝑪+ 𝑨𝑩𝑪+𝑨𝑩𝑪.

285 . The simplified Boolean expression associated with the karnaugh map shown in fig.50 (X indicates ‘don’t care’) is A+BC.

286 . The minimum number of 2-input NAND gates required to implement the function F = (𝑋+ 𝑌) (𝑍+𝑊) is 4.

287 . For the circuit shown below, the output is given by F=0.

288 . The total number of Boolean function which can be realized with four variables is 256.?

289 . The Boolean expression 𝐴.𝐵+𝐴.𝐵+𝐴.𝐵 is equivalent to A+B.

290 . The function generated by the network is (E’+ABF’)(C+D+F’

291 . The Boolean expression for P will be AB.

292 . The Boolean expression for Q will be 𝑨𝑩+ 𝑩𝑨.

293 . The function of the circuit is that of a half adder.

294 . (704)16 = (614)8is incorrect.

295 . The circuit in fig. 54 produces the output sequence 1111 1111 0000 0000.

296 . Match the following
Octal numbers Decimal equivalents
(a) 10 (i) 56
(b) 16 (ii) 14
(c) 7 (iii) 7
(d) 70 (iv) 8
(a)—(iv), (b)—(ii), (c)—(iii), d—(iv)

297 . Match the following

298 . Match the following
Binary numbers Decimal equivalents
(a) 1101 (i) 214
(b) 11011 (ii) 1316
(c) 1.0011 (iii) 27

(d) 10.01 (iv) 13
a—(iv), b—(iii), c—(ii), d—(i)

299 . For the circuit shown below, the output F is given by F=0.

300 . The minimum number of 2-input NAND gates required to implement the function F = (𝑋+𝑌)(𝑍+𝑊)3.