Digital Electronics Objectives Part 25
481 . Content PC after the program is 0115 H.
482 . The value of CY and AC after DDA instruction is 1,1.
483 . Register pairs can be directly stored in memory HL.
484 . The purpose of using ALE signal high is to latch low order address from but o separate A0 – A7 lines.
485 . The purpose of READY signal is it is used to provide for proper WAIT sates when μp is communicating with slow peripheral devices.
486 . The PC contains 0450 H and SP contain 08 D 6 H. the content of Pc and SP following a CALL to subroutine at location 02 AFH is 02 AFH, 08 D 4 H.
487 . The addressing mode used in instruction MOV M, C is indirect.
488 . The addressing mode used in instruction LDA 0345 H is Direct.
489 . The addressing mode used in instruction LXI B 0345 H is immediate.
490 . The first machine cycle of an instruction is always a fetch cycle.
491 . 2 , Fetch and but idle machine cycle needed for execution of MOV A, M.
492 . 1, Fetch machine cycle needed for execution of MOV D,C.
493 . 3, Fetch and memory write machine cycle needed for execution of PUSH B.
494 . 5, Fetch, 2 memory read and 2 memory write are the machine cycle needed for the execution of XTHL.
495 . There are 3 modes of operation in 8255 APPI.
496 . Port—C of 8253 A PPI can be split into two halves.
497 . Group B of ports of 8255 A PPI can be operated in two modes.
498 . the delay between successive bits for 9600 band rate is approximately 0.1 ms is true.
499 . The instruction RIM is equivalent to the instruction IN with one input data line (D7) is true.
500 . SID and SOD lines receive and transmit characters starting from neither D0 nor D0 bit after the START bit.